`include "files/alucode_defines.v"
module wb(
	input				clk,rst,
	input	[31:0]		wb_Addr,
	input	[7:0]		wb_Code,
	input	[31:0]		wb_OData,
	input	[31:0]		wb_RFWAddr,

	output	[31:0]		Addr,
	output	[7:0]		Code,
	output	[31:0]		OData,
	output	[31:0]		RFWAddr

);

reg [31:0]	reg_Addr;
reg [7:0]	reg_Code;
reg [31:0]	reg_OData;
reg [31:0]	reg_RFWAddr;
assign Addr = reg_Addr;
assign Code = reg_Code;
assign OData = reg_OData;
assign RFWAddr = reg_RFWAddr;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		// reset
		reg_Addr <= 0;
		
	end
	else begin
		reg_Addr <= wb_Addr;
		reg_Code <= wb_Code;
		reg_OData <= wb_OData;
		reg_RFWAddr <= wb_RFWAddr;
	end
end
endmodule